Digital cameras, scanners, and other imaging devices often use image sensors, such as charge-coupled device (CCD) image sensors or complementary CMOS image sensors, to convert optical signals to electrical signals. An image sensor typically includes a grid of pixels, row access circuitry, column access circuitry, and a ramp signal generator. The pixels capture the light impinged on them and convert the light signals to electrical signals. The row access circuitry controls which row of pixels that the sensor will read. The column access circuitry includes column read circuits that read the signals from corresponding columns. The ramp signal generator generates a ramping signal as a global reference signal for column read circuits to record the converted electrical signal. In operation, the quality of the ramping signal can significantly affect the quality of the output of the image sensor.
In conventional CMOS Image sensing, a ramp voltage wave signal (“vramp signal”) is used as the global reference for an Analog-to-Digital Converter (ADC) circuit. In this case, vramp usually ramps up linearly before quickly dropping to zero and repeats this cycle. Such ADC is known as Ramp-ADC (or Ramp-Compare-ADC), which can convert analog signals from photodiode pixels into digital codes. The ramp time of the vramp signal travelling across the photodiode signal is correlated with the light strength. For a positive ramp, a ramp crossing time is shorter in weak light areas, and longer in strong light areas. The least significant bit (LSB) voltage of a Ramp-ADC is unchangeable in both weak light areas and strong light areas because of the linearity of vramp signals. The dynamic range (DR) of image sensors is limited by a resolution of a Ramp-ADC, DR=FSR/LSB=2N=6.02N (dB), where FSR is a full-scale rage or the maximum value of the input voltage of the Ramp-ADC, and LSB is the minimum input that the ADC can sense, also known as the resolution of the ADC. Thus, DR can represent a range of signal amplitudes which the ADC can resolve. To improve the sensor performance by increasing DR, FSR can be increased or LSB can be decreased.
Current extended dynamic range or high dynamic range (HDR) image sensors often use the multi-exposure technology or extend the ADC bits. With regard to the multi-exposure technology, the sensors capture several pictures with different exposure times. A backend software or an image signal processor (ISP) merges all the captured pictures together to generate a HDR picture. This technology has at least three drawbacks. The first drawback is having a low picture clarity. Because these pictures with different exposure times are taken at different time points, both the target and the camera may be shifted. The merged picture can be unclear. The second drawback is having a low speed. Merging several high resolution pictures together needs a long computing time. The third drawback is having a high cost. To merge several high resolution pictures, a sophisticated software or ISP is needed. A fast temporary memory is required to save raw picture data. Thus, the system cost can be too high to get a fast frame rate and high resolution HDR pictures. With regard to the ADC bits-extending technology, sensor frame rate may be adversely affected. For example, if the bits number of ADC increases from 10 bits to 12 bits, the sensor will need four times of ramping time, and the speed becomes a limitation. The disclosed systems and methods may mitigate or overcome one or more of the problems set forth above and/or other problems in the prior art.